Periodic digital signals are commonly used in a variety of electronic devices. Probably the most common type of periodic digital signals are clock signals that are typically used to establish the timing of a digital signal or the timing at which an operation is performed on a digital signal. For example, data signals are typically coupled to and from memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, in synchronism with a clock or data strobe signal. More specifically, read data signals are typically coupled from a memory device in synchronism with a read data strobe signal, and write data signals are typically latched into a memory device in synchronism with a write data strobe signal. The read data strobe signal typically has the same phase as the read data signals, and it is normally generated by the same device that generates the read data signals. As a result, it is relatively easy to generate a read data strobe signal.
Unlike a read data strobe signal, a write data strobe signal normally must have a phase that is the quadrature of the write data signals so that a transition of the write data strobe signal occurs during a “data eye” occurring at the center of the period in which the write data signals are valid. However, as the speed of memory devices has continued to increase, the “data eye” has become smaller and smaller, thus making the timing of the write data strobe signal even more critical.
The write strobe signal is typically generated by the memory controller from a system clock signal and it is coupled to the memory device into which the data are being written. Unfortunately, the phase of the system clock signal is normally substantially the same as the phase of the write data signals. Therefore, it is necessary for the memory controller to generate the write data strobe signal as a quadrature signal having a phase that is 90-degrees relative to the phase of the system clock signal.
Various techniques can be used and have been used by memory devices to generate a quadrature write data strobe signal. If the frequency of the system clock signal is fixed, a quadrature write strobe signal can be generated by a timing circuit that simply generates a transition of the write strobe signal a fixed time after a corresponding transition of the system clock signal. However, synchronous memory devices are typically designed and sold to be operated over a wide range of system clock frequencies. Therefore, it is generally not practical to use a fixed timing circuit to generate a write data strobe signal from the system clock signal. Instead, a circuit that can adapt itself to a system clock signal having a range of frequencies must be used.
One conventional circuit that can generate a quadrature write data strobe signal from a system clock signal having a variable frequency is a phase-lock loop in which a voltage controlled oscillator generates a signal that is coupled to a phase detector along with the master clock signal. The phase detector generates an error signal that is used to control the frequency of the signal generated by the voltage controlled oscillator. Various signal processing techniques can be used to generate a quadrature signal from the signal generated by the voltage controlled oscillator.
Closed loop circuits, such as phase-lock loops and delay-lock loops, can accurately generate a quadrature write strobe signal based on the system clock signal over a substantial range of frequencies of the system clock signal. However, closed loop circuits are not without their disadvantages and limitations. Specifically, closed loop circuits typically require a substantial amount of circuitry, which occupies space on a semiconductor die that could otherwise be used for increased memory capacity. Furthermore, it typically requires a substantial period of time for the closed loop circuit to establish “lock” during which time the memory device cannot latch write data signals.
Quadrature digital signals are also required for applications other than for use as a write data strobe signal. For example, a “frequency doubler” circuit, which generates an output clock signal having twice the frequency of an input clock signal, can be implemented using an appropriate logic circuit that receives the input clock signal and quadrature versions of the input clock signal. However, generating the necessary quadrature clock signal has the same type of difficulties that are incurred in generating a quadrature write data strobe signal.
The limitations and disadvantages of conventional closed-loop clock generating circuit, such as phase-lock loops and delay-lock loops, have been addressed by an open loop system described in U.S. patent application Ser. No. 10/854,849 to Zimlich. Briefly, an input clock signal propagates through a measurement delay line having a plurality of delay elements. The delay element to which a transition, e.g., the rising edge, of the input clock signal has propagated at the next transition of the input clock signal (i.e., one period after the start of the clock pulse) sets a bit in corresponding delay element of a signal generating delay line having a sub-multiple of the number of delay elements. The set bit then propagates through the signal generating delay line. If, for example, the measurement delay line has twice as many delay elements as the signal generating delay line, the signal propagating through the signal generating delay line will be output one-half period after the start of each input clock signal. If the measurement delay line has four times as many delay elements as the signal generating delay line, the signal propagating through the signal generating delay line will be output one-quarter period after the start of each input clock signal. By using multiple signal delay lines each having a different sub-multiple number of delay elements compared to the number delay elements in the measurement delay line, any number of different phases of the input clock signal can be generated.
Although this open loop clock generating system avoids many of the disadvantages of closed-loop clock generating systems, it has the disadvantage of consuming a considerable amount of power. The high power consumption is, in part, the result of the power consumed by each cycle of the input clock signal propagating through the measurement delay line. The power consumed by the measurement delay line is particularly high because the measurement delay line contains a large number of delay elements, each of which consumes power each time it switches.
There is therefore a need for an open loop system and method for generating a periodic signal having a selected phase relative to another periodic signal that consumes a relatively little amount of power.